8000 /*	$NetBSD: pcireg.h,v 1.45 2004/02/04 06:58:24 soren Exp $	*/
8001 
8002 /*
8003  * Copyright (c) 1995, 1996, 1999, 2000
8004  *     Christopher G. Demetriou.  All rights reserved.
8005  * Copyright (c) 1994, 1996 Charles M. Hannum.  All rights reserved.
8006  *
8007  * Redistribution and use in source and binary forms, with or without
8008  * modification, are permitted provided that the following conditions
8009  * are met:
8010  * 1. Redistributions of source code must retain the above copyright
8011  *    notice, this list of conditions and the following disclaimer.
8012  * 2. Redistributions in binary form must reproduce the above copyright
8013  *    notice, this list of conditions and the following disclaimer in the
8014  *    documentation and/or other materials provided with the distribution.
8015  * 3. All advertising materials mentioning features or use of this software
8016  *    must display the following acknowledgement:
8017  *	This product includes software developed by Charles M. Hannum.
8018  * 4. The name of the author may not be used to endorse or promote products
8019  *    derived from this software without specific prior written permission.
8020  *
8021  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
8022  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8023  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
8024  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8025  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8026  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
8027  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
8028  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8029  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8030  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8031  */
8032 
8033 #ifndef _DEV_PCI_PCIREG_H_
8034 #define	_DEV_PCI_PCIREG_H_
8035 
8036 /*
8037  * Standardized PCI configuration information
8038  *
8039  * XXX This is not complete.
8040  */
8041 
8042 #include "types.h"
8043 
8044 /*
8045  * Device identification register; contains a vendor ID and a device ID.
8046  */
8047 #define	PCI_ID_REG			0x00
8048 
8049 
8050 typedef uint16_t pci_vendor_id_t;
8051 typedef uint16_t pci_product_id_t;
8052 
8053 #define	PCI_VENDOR_SHIFT			0
8054 #define	PCI_VENDOR_MASK				0xffff
8055 #define	PCI_VENDOR(id) \
8056 	    (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)
8057 
8058 #define	PCI_PRODUCT_SHIFT			16
8059 #define	PCI_PRODUCT_MASK			0xffff
8060 #define	PCI_PRODUCT(id) \
8061 	    (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)
8062 
8063 #define PCI_ID_CODE(vid,pid)					\
8064 	((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) |	\
8065 	 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT))	\
8066 
8067 /*
8068  * Command and status register.
8069  */
8070 #define	PCI_COMMAND_STATUS_REG			0x04
8071 #define	PCI_COMMAND_SHIFT			0
8072 #define	PCI_COMMAND_MASK			0xffff
8073 #define	PCI_STATUS_SHIFT			16
8074 #define	PCI_STATUS_MASK				0xffff
8075 
8076 #define PCI_COMMAND_STATUS_CODE(cmd,stat)			\
8077 	((((cmd) & PCI_COMMAND_MASK) >> PCI_COMMAND_SHIFT) |	\
8078 	 (((stat) & PCI_STATUS_MASK) >> PCI_STATUS_SHIFT))	\
8079 
8080 #define	PCI_COMMAND_IO_ENABLE			0x00000001
8081 #define	PCI_COMMAND_MEM_ENABLE			0x00000002
8082 #define	PCI_COMMAND_MASTER_ENABLE		0x00000004
8083 #define	PCI_COMMAND_SPECIAL_ENABLE		0x00000008
8084 #define	PCI_COMMAND_INVALIDATE_ENABLE		0x00000010
8085 #define	PCI_COMMAND_PALETTE_ENABLE		0x00000020
8086 #define	PCI_COMMAND_PARITY_ENABLE		0x00000040
8087 #define	PCI_COMMAND_STEPPING_ENABLE		0x00000080
8088 #define	PCI_COMMAND_SERR_ENABLE			0x00000100
8089 #define	PCI_COMMAND_BACKTOBACK_ENABLE		0x00000200
8090 
8091 #define	PCI_STATUS_CAPLIST_SUPPORT		0x00100000
8092 #define	PCI_STATUS_66MHZ_SUPPORT		0x00200000
8093 #define	PCI_STATUS_UDF_SUPPORT			0x00400000
8094 #define	PCI_STATUS_BACKTOBACK_SUPPORT		0x00800000
8095 #define	PCI_STATUS_PARITY_ERROR			0x01000000
8096 #define	PCI_STATUS_DEVSEL_FAST			0x00000000
8097 #define	PCI_STATUS_DEVSEL_MEDIUM		0x02000000
8098 #define	PCI_STATUS_DEVSEL_SLOW			0x04000000
8099 #define	PCI_STATUS_DEVSEL_MASK			0x06000000
8100 #define	PCI_STATUS_TARGET_TARGET_ABORT		0x08000000
8101 #define	PCI_STATUS_MASTER_TARGET_ABORT		0x10000000
8102 #define	PCI_STATUS_MASTER_ABORT			0x20000000
8103 #define	PCI_STATUS_SPECIAL_ERROR		0x40000000
8104 #define	PCI_STATUS_PARITY_DETECT		0x80000000
8105 
8106 /*
8107  * PCI Class and Revision Register; defines type and revision of device.
8108  */
8109 #define	PCI_CLASS_REG			0x08
8110 
8111 typedef uint8_t pci_class_t;
8112 typedef uint8_t pci_subclass_t;
8113 typedef uint8_t pci_interface_t;
8114 typedef uint8_t pci_revision_t;
8115 
8116 #define	PCI_CLASS_SHIFT				24
8117 #define	PCI_CLASS_MASK				0xff
8118 #define	PCI_CLASS(cr) \
8119 	    (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
8120 
8121 #define	PCI_SUBCLASS_SHIFT			16
8122 #define	PCI_SUBCLASS_MASK			0xff
8123 #define	PCI_SUBCLASS(cr) \
8124 	    (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
8125 
8126 #define	PCI_INTERFACE_SHIFT			8
8127 #define	PCI_INTERFACE_MASK			0xff
8128 #define	PCI_INTERFACE(cr) \
8129 	    (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
8130 
8131 #define	PCI_REVISION_SHIFT			0
8132 #define	PCI_REVISION_MASK			0xff
8133 #define	PCI_REVISION(cr) \
8134 	    (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
8135 
8136 #define	PCI_CLASS_CODE(mainclass, subclass, interface) \
8137 	    ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \
8138 	     (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \
8139 	     (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT))
8140 
8141 /* base classes */
8142 #define	PCI_CLASS_PREHISTORIC			0x00
8143 #define	PCI_CLASS_MASS_STORAGE			0x01
8144 #define	PCI_CLASS_NETWORK			0x02
8145 #define	PCI_CLASS_DISPLAY			0x03
8146 #define	PCI_CLASS_MULTIMEDIA			0x04
8147 #define	PCI_CLASS_MEMORY			0x05
8148 #define	PCI_CLASS_BRIDGE			0x06
8149 #define	PCI_CLASS_COMMUNICATIONS		0x07
8150 #define	PCI_CLASS_SYSTEM			0x08
8151 #define	PCI_CLASS_INPUT				0x09
8152 #define	PCI_CLASS_DOCK				0x0a
8153 #define	PCI_CLASS_PROCESSOR			0x0b
8154 #define	PCI_CLASS_SERIALBUS			0x0c
8155 #define	PCI_CLASS_WIRELESS			0x0d
8156 #define	PCI_CLASS_I2O				0x0e
8157 #define	PCI_CLASS_SATCOM			0x0f
8158 #define	PCI_CLASS_CRYPTO			0x10
8159 #define	PCI_CLASS_DASP				0x11
8160 #define	PCI_CLASS_UNDEFINED			0xff
8161 
8162 /* 0x00 prehistoric subclasses */
8163 #define	PCI_SUBCLASS_PREHISTORIC_MISC		0x00
8164 #define	PCI_SUBCLASS_PREHISTORIC_VGA		0x01
8165 
8166 /* 0x01 mass storage subclasses */
8167 #define	PCI_SUBCLASS_MASS_STORAGE_SCSI		0x00
8168 #define	PCI_SUBCLASS_MASS_STORAGE_IDE		0x01
8169 #define	PCI_SUBCLASS_MASS_STORAGE_FLOPPY	0x02
8170 #define	PCI_SUBCLASS_MASS_STORAGE_IPI		0x03
8171 #define	PCI_SUBCLASS_MASS_STORAGE_RAID		0x04
8172 #define	PCI_SUBCLASS_MASS_STORAGE_ATA		0x05
8173 #define	PCI_SUBCLASS_MASS_STORAGE_SATA		0x06
8174 #define	PCI_SUBCLASS_MASS_STORAGE_MISC		0x80
8175 
8176 /* 0x02 network subclasses */
8177 #define	PCI_SUBCLASS_NETWORK_ETHERNET		0x00
8178 #define	PCI_SUBCLASS_NETWORK_TOKENRING		0x01
8179 #define	PCI_SUBCLASS_NETWORK_FDDI		0x02
8180 #define	PCI_SUBCLASS_NETWORK_ATM		0x03
8181 #define	PCI_SUBCLASS_NETWORK_ISDN		0x04
8182 #define	PCI_SUBCLASS_NETWORK_WORLDFIP		0x05
8183 #define	PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP	0x06
8184 #define	PCI_SUBCLASS_NETWORK_MISC		0x80
8185 
8186 /* 0x03 display subclasses */
8187 #define	PCI_SUBCLASS_DISPLAY_VGA		0x00
8188 #define	PCI_SUBCLASS_DISPLAY_XGA		0x01
8189 #define	PCI_SUBCLASS_DISPLAY_3D			0x02
8190 #define	PCI_SUBCLASS_DISPLAY_MISC		0x80
8191 
8192 /* 0x04 multimedia subclasses */
8193 #define	PCI_SUBCLASS_MULTIMEDIA_VIDEO		0x00
8194 #define	PCI_SUBCLASS_MULTIMEDIA_AUDIO		0x01
8195 #define	PCI_SUBCLASS_MULTIMEDIA_TELEPHONY	0x02
8196 #define	PCI_SUBCLASS_MULTIMEDIA_MISC		0x80
8197 
8198 
8199 
8200 /* 0x05 memory subclasses */
8201 #define	PCI_SUBCLASS_MEMORY_RAM			0x00
8202 #define	PCI_SUBCLASS_MEMORY_FLASH		0x01
8203 #define	PCI_SUBCLASS_MEMORY_MISC		0x80
8204 
8205 /* 0x06 bridge subclasses */
8206 #define	PCI_SUBCLASS_BRIDGE_HOST		0x00
8207 #define	PCI_SUBCLASS_BRIDGE_ISA			0x01
8208 #define	PCI_SUBCLASS_BRIDGE_EISA		0x02
8209 #define	PCI_SUBCLASS_BRIDGE_MC			0x03	/* XXX _MCA? */
8210 #define	PCI_SUBCLASS_BRIDGE_PCI			0x04
8211 #define	PCI_SUBCLASS_BRIDGE_PCMCIA		0x05
8212 #define	PCI_SUBCLASS_BRIDGE_NUBUS		0x06
8213 #define	PCI_SUBCLASS_BRIDGE_CARDBUS		0x07
8214 #define	PCI_SUBCLASS_BRIDGE_RACEWAY		0x08
8215 #define	PCI_SUBCLASS_BRIDGE_STPCI		0x09
8216 #define	PCI_SUBCLASS_BRIDGE_INFINIBAND		0x0a
8217 #define	PCI_SUBCLASS_BRIDGE_MISC		0x80
8218 
8219 /* 0x07 communications subclasses */
8220 #define	PCI_SUBCLASS_COMMUNICATIONS_SERIAL	0x00
8221 #define	PCI_SUBCLASS_COMMUNICATIONS_PARALLEL	0x01
8222 #define	PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL	0x02
8223 #define	PCI_SUBCLASS_COMMUNICATIONS_MODEM	0x03
8224 #define	PCI_SUBCLASS_COMMUNICATIONS_GPIB	0x04
8225 #define	PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD	0x05
8226 #define	PCI_SUBCLASS_COMMUNICATIONS_MISC	0x80
8227 
8228 /* 0x08 system subclasses */
8229 #define	PCI_SUBCLASS_SYSTEM_PIC			0x00
8230 #define	PCI_SUBCLASS_SYSTEM_DMA			0x01
8231 #define	PCI_SUBCLASS_SYSTEM_TIMER		0x02
8232 #define	PCI_SUBCLASS_SYSTEM_RTC			0x03
8233 #define	PCI_SUBCLASS_SYSTEM_PCIHOTPLUG		0x04
8234 #define	PCI_SUBCLASS_SYSTEM_MISC		0x80
8235 
8236 /* 0x09 input subclasses */
8237 #define	PCI_SUBCLASS_INPUT_KEYBOARD		0x00
8238 #define	PCI_SUBCLASS_INPUT_DIGITIZER		0x01
8239 #define	PCI_SUBCLASS_INPUT_MOUSE		0x02
8240 #define	PCI_SUBCLASS_INPUT_SCANNER		0x03
8241 #define	PCI_SUBCLASS_INPUT_GAMEPORT		0x04
8242 #define	PCI_SUBCLASS_INPUT_MISC			0x80
8243 
8244 /* 0x0a dock subclasses */
8245 #define	PCI_SUBCLASS_DOCK_GENERIC		0x00
8246 #define	PCI_SUBCLASS_DOCK_MISC			0x80
8247 
8248 
8249 
8250 /* 0x0b processor subclasses */
8251 #define	PCI_SUBCLASS_PROCESSOR_386		0x00
8252 #define	PCI_SUBCLASS_PROCESSOR_486		0x01
8253 #define	PCI_SUBCLASS_PROCESSOR_PENTIUM		0x02
8254 #define	PCI_SUBCLASS_PROCESSOR_ALPHA		0x10
8255 #define	PCI_SUBCLASS_PROCESSOR_POWERPC		0x20
8256 #define	PCI_SUBCLASS_PROCESSOR_MIPS		0x30
8257 #define	PCI_SUBCLASS_PROCESSOR_COPROC		0x40
8258 
8259 /* 0x0c serial bus subclasses */
8260 #define	PCI_SUBCLASS_SERIALBUS_FIREWIRE		0x00
8261 #define	PCI_SUBCLASS_SERIALBUS_ACCESS		0x01
8262 #define	PCI_SUBCLASS_SERIALBUS_SSA		0x02
8263 #define	PCI_SUBCLASS_SERIALBUS_USB		0x03
8264 #define	PCI_SUBCLASS_SERIALBUS_FIBER		0x04	/* XXX _FIBRECHANNEL */
8265 #define	PCI_SUBCLASS_SERIALBUS_SMBUS		0x05
8266 #define	PCI_SUBCLASS_SERIALBUS_INFINIBAND	0x06
8267 #define	PCI_SUBCLASS_SERIALBUS_IPMI		0x07
8268 #define	PCI_SUBCLASS_SERIALBUS_SERCOS		0x08
8269 #define	PCI_SUBCLASS_SERIALBUS_CANBUS		0x09
8270 
8271 /* 0x0d wireless subclasses */
8272 #define	PCI_SUBCLASS_WIRELESS_IRDA		0x00
8273 #define	PCI_SUBCLASS_WIRELESS_CONSUMERIR	0x01
8274 #define	PCI_SUBCLASS_WIRELESS_RF		0x10
8275 #define	PCI_SUBCLASS_WIRELESS_BLUETOOTH		0x11
8276 #define	PCI_SUBCLASS_WIRELESS_BROADBAND		0x12
8277 #define	PCI_SUBCLASS_WIRELESS_802_11A		0x20
8278 #define	PCI_SUBCLASS_WIRELESS_802_11B		0x21
8279 #define	PCI_SUBCLASS_WIRELESS_MISC		0x80
8280 
8281 /* 0x0e I2O (Intelligent I/O) subclasses */
8282 #define	PCI_SUBCLASS_I2O_STANDARD		0x00
8283 
8284 /* 0x0f satellite communication subclasses */
8285 /*	PCI_SUBCLASS_SATCOM_???			0x00	/ * XXX ??? */
8286 #define	PCI_SUBCLASS_SATCOM_TV			0x01
8287 #define	PCI_SUBCLASS_SATCOM_AUDIO		0x02
8288 #define	PCI_SUBCLASS_SATCOM_VOICE		0x03
8289 #define	PCI_SUBCLASS_SATCOM_DATA		0x04
8290 
8291 /* 0x10 encryption/decryption subclasses */
8292 #define	PCI_SUBCLASS_CRYPTO_NETCOMP		0x00
8293 #define	PCI_SUBCLASS_CRYPTO_ENTERTAINMENT	0x10
8294 #define	PCI_SUBCLASS_CRYPTO_MISC		0x80
8295 
8296 
8297 
8298 
8299 
8300 /* 0x11 data acquisition and signal processing subclasses */
8301 #define	PCI_SUBCLASS_DASP_DPIO			0x00
8302 #define	PCI_SUBCLASS_DASP_TIMEFREQ		0x01
8303 #define	PCI_SUBCLASS_DASP_SYNC			0x10
8304 #define	PCI_SUBCLASS_DASP_MGMT			0x20
8305 #define	PCI_SUBCLASS_DASP_MISC			0x80
8306 
8307 /*
8308  * PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
8309  */
8310 #define	PCI_BHLC_REG			0x0c
8311 
8312 #define	PCI_BIST_SHIFT				24
8313 #define	PCI_BIST_MASK				0xff
8314 #define	PCI_BIST(bhlcr) \
8315 	    (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
8316 
8317 #define	PCI_HDRTYPE_SHIFT			16
8318 #define	PCI_HDRTYPE_MASK			0xff
8319 #define	PCI_HDRTYPE(bhlcr) \
8320 	    (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
8321 
8322 #define	PCI_HDRTYPE_TYPE(bhlcr) \
8323 	    (PCI_HDRTYPE(bhlcr) & 0x7f)
8324 #define	PCI_HDRTYPE_MULTIFN(bhlcr) \
8325 	    ((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
8326 
8327 #define	PCI_LATTIMER_SHIFT			8
8328 #define	PCI_LATTIMER_MASK			0xff
8329 #define	PCI_LATTIMER(bhlcr) \
8330 	    (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
8331 
8332 #define	PCI_CACHELINE_SHIFT			0
8333 #define	PCI_CACHELINE_MASK			0xff
8334 #define	PCI_CACHELINE(bhlcr) \
8335 	    (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
8336 
8337 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline)		\
8338 	    ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) |		\
8339 	     (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) |	\
8340 	     (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) |			\
8341 	     (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) |	\
8342 	     (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT))
8343 
8344 /*
8345  * PCI header type
8346  */
8347 #define PCI_HDRTYPE_DEVICE	0
8348 #define PCI_HDRTYPE_PPB		1
8349 #define PCI_HDRTYPE_PCB		2
8350 /*
8351  * Mapping registers
8352  */
8353 #define	PCI_MAPREG_START		0x10
8354 #define	PCI_MAPREG_END			0x28
8355 #define	PCI_MAPREG_ROM			0x30
8356 #define	PCI_MAPREG_PPB_END		0x18
8357 #define	PCI_MAPREG_PCB_END		0x14
8358 
8359 #define	PCI_MAPREG_TYPE(mr)						\
8360 	    ((mr) & PCI_MAPREG_TYPE_MASK)
8361 #define	PCI_MAPREG_TYPE_MASK			0x00000001
8362 
8363 #define	PCI_MAPREG_TYPE_MEM			0x00000000
8364 #define	PCI_MAPREG_TYPE_IO			0x00000001
8365 #define	PCI_MAPREG_ROM_ENABLE			0x00000001
8366 
8367 #define	PCI_MAPREG_MEM_TYPE(mr)						\
8368 	    ((mr) & PCI_MAPREG_MEM_TYPE_MASK)
8369 #define	PCI_MAPREG_MEM_TYPE_MASK		0x00000006
8370 
8371 #define	PCI_MAPREG_MEM_TYPE_32BIT		0x00000000
8372 #define	PCI_MAPREG_MEM_TYPE_32BIT_1M		0x00000002
8373 #define	PCI_MAPREG_MEM_TYPE_64BIT		0x00000004
8374 
8375 #define	PCI_MAPREG_MEM_PREFETCHABLE(mr)				\
8376 	    (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)
8377 #define	PCI_MAPREG_MEM_PREFETCHABLE_MASK	0x00000008
8378 
8379 #define	PCI_MAPREG_MEM_ADDR(mr)						\
8380 	    ((mr) & PCI_MAPREG_MEM_ADDR_MASK)
8381 #define	PCI_MAPREG_MEM_SIZE(mr)						\
8382 	    (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
8383 #define	PCI_MAPREG_MEM_ADDR_MASK		0xfffffff0
8384 
8385 #define	PCI_MAPREG_MEM64_ADDR(mr)					\
8386 	    ((mr) & PCI_MAPREG_MEM64_ADDR_MASK)
8387 #define	PCI_MAPREG_MEM64_SIZE(mr)					\
8388 	    (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))
8389 #define	PCI_MAPREG_MEM64_ADDR_MASK		0xfffffffffffffff0ULL
8390 
8391 #define	PCI_MAPREG_IO_ADDR(mr)						\
8392 	    ((mr) & PCI_MAPREG_IO_ADDR_MASK)
8393 #define	PCI_MAPREG_IO_SIZE(mr)						\
8394 	    (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
8395 #define	PCI_MAPREG_IO_ADDR_MASK			0xfffffffc
8396 
8397 #define PCI_MAPREG_SIZE_TO_MASK(size)					\
8398 	    (-(size))
8399 
8400 #define PCI_MAPREG_NUM(offset)						\
8401 	    (((unsigned)(offset)-PCI_MAPREG_START)/4)
8402 
8403 
8404 /*
8405  * Cardbus CIS pointer (PCI rev. 2.1)
8406  */
8407 #define PCI_CARDBUS_CIS_REG 0x28
8408 
8409 /*
8410  * Subsystem identification register; contains a vendor ID and a device ID.
8411  * Types/macros for PCI_ID_REG apply.
8412  * (PCI rev. 2.1)
8413  */
8414 #define PCI_SUBSYS_ID_REG 0x2c
8415 
8416 /*
8417  * Capabilities link list (PCI rev. 2.2)
8418  */
8419 #define	PCI_CAPLISTPTR_REG		0x34	/* header type 0 */
8420 #define	PCI_CARDBUS_CAPLISTPTR_REG	0x14	/* header type 2 */
8421 #define	PCI_CAPLIST_PTR(cpr)	((cpr) & 0xff)
8422 #define	PCI_CAPLIST_NEXT(cr)	(((cr) >> 8) & 0xff)
8423 #define	PCI_CAPLIST_CAP(cr)	((cr) & 0xff)
8424 
8425 #define	PCI_CAP_RESERVED0	0x00
8426 #define	PCI_CAP_PWRMGMT		0x01
8427 #define	PCI_CAP_AGP		0x02
8428 #define PCI_CAP_AGP_MAJOR(cr)	(((cr) >> 20) & 0xf)
8429 #define PCI_CAP_AGP_MINOR(cr)	(((cr) >> 16) & 0xf)
8430 #define	PCI_CAP_VPD		0x03
8431 #define	PCI_CAP_SLOTID		0x04
8432 #define	PCI_CAP_MSI		0x05
8433 #define	PCI_CAP_CPCI_HOTSWAP	0x06
8434 #define	PCI_CAP_PCIX		0x07
8435 #define	PCI_CAP_LDT		0x08
8436 #define	PCI_CAP_VENDSPEC	0x09
8437 #define	PCI_CAP_DEBUGPORT	0x0a
8438 #define	PCI_CAP_CPCI_RSRCCTL	0x0b
8439 #define	PCI_CAP_HOTPLUG		0x0c
8440 #define	PCI_CAP_AGP8		0x0e
8441 #define	PCI_CAP_SECURE		0x0f
8442 #define	PCI_CAP_PCIEXPRESS     	0x10
8443 #define	PCI_CAP_MSIX		0x11
8444 
8445 /*
8446  * Vital Product Data; access via capability pointer (PCI rev 2.2).
8447  */
8448 #define	PCI_VPD_ADDRESS_MASK	0x7fff
8449 #define	PCI_VPD_ADDRESS_SHIFT	16
8450 #define	PCI_VPD_ADDRESS(ofs)	\
8451 	(((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT)
8452 #define	PCI_VPD_DATAREG(ofs)	((ofs) + 4)
8453 #define	PCI_VPD_OPFLAG		0x80000000
8454 
8455 /*
8456  * Power Management Capability; access via capability pointer.
8457  */
8458 
8459 /* Power Management Capability Register */
8460 #define PCI_PMCR		0x02
8461 #define PCI_PMCR_D1SUPP		0x0200
8462 #define PCI_PMCR_D2SUPP		0x0400
8463 /* Power Management Control Status Register */
8464 #define PCI_PMCSR		0x04
8465 #define PCI_PMCSR_STATE_MASK	0x03
8466 #define PCI_PMCSR_STATE_D0      0x00
8467 #define PCI_PMCSR_STATE_D1      0x01
8468 #define PCI_PMCSR_STATE_D2      0x02
8469 #define PCI_PMCSR_STATE_D3      0x03
8470 
8471 /*
8472  * PCI-X capability.
8473  */
8474 
8475 /*
8476  * Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit
8477  * word at the capability; the lower 16 bits are the capability ID and
8478  * next capability pointer).
8479  *
8480  * Since we always read PCI config space in 32-bit words, we define these
8481  * as 32-bit values, offset and shifted appropriately.  Make sure you perform
8482  * the appropriate R/M/W cycles!
8483  */
8484 #define PCI_PCIX_CMD			0x00
8485 #define PCI_PCIX_CMD_PERR_RECOVER	0x00010000
8486 #define PCI_PCIX_CMD_RELAXED_ORDER	0x00020000
8487 #define PCI_PCIX_CMD_BYTECNT_MASK	0x000c0000
8488 #define	PCI_PCIX_CMD_BYTECNT_SHIFT	18
8489 #define		PCI_PCIX_CMD_BCNT_512		0x00000000
8490 #define		PCI_PCIX_CMD_BCNT_1024		0x00040000
8491 #define		PCI_PCIX_CMD_BCNT_2048		0x00080000
8492 #define		PCI_PCIX_CMD_BCNT_4096		0x000c0000
8493 #define PCI_PCIX_CMD_SPLTRANS_MASK	0x00700000
8494 #define		PCI_PCIX_CMD_SPLTRANS_1		0x00000000
8495 #define		PCI_PCIX_CMD_SPLTRANS_2		0x00100000
8496 #define		PCI_PCIX_CMD_SPLTRANS_3		0x00200000
8497 #define		PCI_PCIX_CMD_SPLTRANS_4		0x00300000
8498 #define		PCI_PCIX_CMD_SPLTRANS_8		0x00400000
8499 #define		PCI_PCIX_CMD_SPLTRANS_12	0x00500000
8500 #define		PCI_PCIX_CMD_SPLTRANS_16	0x00600000
8501 #define		PCI_PCIX_CMD_SPLTRANS_32	0x00700000
8502 
8503 /*
8504  * Status. 32 bits at offset 4.
8505  */
8506 #define PCI_PCIX_STATUS			0x04
8507 #define PCI_PCIX_STATUS_FN_MASK		0x00000007
8508 #define PCI_PCIX_STATUS_DEV_MASK	0x000000f8
8509 #define PCI_PCIX_STATUS_BUS_MASK	0x0000ff00
8510 #define PCI_PCIX_STATUS_64BIT		0x00010000
8511 #define PCI_PCIX_STATUS_133		0x00020000
8512 #define PCI_PCIX_STATUS_SPLDISC		0x00040000
8513 #define PCI_PCIX_STATUS_SPLUNEX		0x00080000
8514 #define PCI_PCIX_STATUS_DEVCPLX		0x00100000
8515 #define PCI_PCIX_STATUS_MAXB_MASK	0x00600000
8516 #define	PCI_PCIX_STATUS_MAXB_SHIFT	21
8517 #define		PCI_PCIX_STATUS_MAXB_512	0x00000000
8518 #define		PCI_PCIX_STATUS_MAXB_1024	0x00200000
8519 #define		PCI_PCIX_STATUS_MAXB_2048	0x00400000
8520 #define		PCI_PCIX_STATUS_MAXB_4096	0x00600000
8521 #define PCI_PCIX_STATUS_MAXST_MASK	0x03800000
8522 #define		PCI_PCIX_STATUS_MAXST_1		0x00000000
8523 #define		PCI_PCIX_STATUS_MAXST_2		0x00800000
8524 #define		PCI_PCIX_STATUS_MAXST_3		0x01000000
8525 #define		PCI_PCIX_STATUS_MAXST_4		0x01800000
8526 #define		PCI_PCIX_STATUS_MAXST_8		0x02000000
8527 #define		PCI_PCIX_STATUS_MAXST_12	0x02800000
8528 #define		PCI_PCIX_STATUS_MAXST_16	0x03000000
8529 #define		PCI_PCIX_STATUS_MAXST_32	0x03800000
8530 #define PCI_PCIX_STATUS_MAXRS_MASK	0x1c000000
8531 #define		PCI_PCIX_STATUS_MAXRS_1K	0x00000000
8532 #define		PCI_PCIX_STATUS_MAXRS_2K	0x04000000
8533 #define		PCI_PCIX_STATUS_MAXRS_4K	0x08000000
8534 #define		PCI_PCIX_STATUS_MAXRS_8K	0x0c000000
8535 #define		PCI_PCIX_STATUS_MAXRS_16K	0x10000000
8536 #define		PCI_PCIX_STATUS_MAXRS_32K	0x14000000
8537 #define		PCI_PCIX_STATUS_MAXRS_64K	0x18000000
8538 #define		PCI_PCIX_STATUS_MAXRS_128K	0x1c000000
8539 #define PCI_PCIX_STATUS_SCERR			0x20000000
8540 
8541 
8542 /*
8543  * Interrupt Configuration Register; contains interrupt pin and line.
8544  */
8545 #define	PCI_INTERRUPT_REG		0x3c
8546 
8547 
8548 
8549 
8550 typedef uint8_t pci_intr_latency_t;
8551 typedef uint8_t pci_intr_grant_t;
8552 typedef uint8_t pci_intr_pin_t;
8553 typedef uint8_t pci_intr_line_t;
8554 
8555 #define PCI_MAX_LAT_SHIFT			24
8556 #define	PCI_MAX_LAT_MASK			0xff
8557 #define	PCI_MAX_LAT(icr) \
8558 	    (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK)
8559 
8560 #define PCI_MIN_GNT_SHIFT			16
8561 #define	PCI_MIN_GNT_MASK			0xff
8562 #define	PCI_MIN_GNT(icr) \
8563 	    (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK)
8564 
8565 #define	PCI_INTERRUPT_GRANT_SHIFT		24
8566 #define	PCI_INTERRUPT_GRANT_MASK		0xff
8567 #define	PCI_INTERRUPT_GRANT(icr) \
8568 	    (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK)
8569 
8570 #define	PCI_INTERRUPT_LATENCY_SHIFT		16
8571 #define	PCI_INTERRUPT_LATENCY_MASK		0xff
8572 #define	PCI_INTERRUPT_LATENCY(icr) \
8573 	    (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK)
8574 
8575 #define	PCI_INTERRUPT_PIN_SHIFT			8
8576 #define	PCI_INTERRUPT_PIN_MASK			0xff
8577 #define	PCI_INTERRUPT_PIN(icr) \
8578 	    (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)
8579 
8580 #define	PCI_INTERRUPT_LINE_SHIFT		0
8581 #define	PCI_INTERRUPT_LINE_MASK			0xff
8582 #define	PCI_INTERRUPT_LINE(icr) \
8583 	    (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)
8584 
8585 #define PCI_INTERRUPT_CODE(lat,gnt,pin,line)		\
8586 	  ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \
8587 	   (((gnt)&PCI_INTERRUPT_GRANT_MASK)  <<PCI_INTERRUPT_GRANT_SHIFT)  | \
8588 	   (((pin)&PCI_INTERRUPT_PIN_MASK)    <<PCI_INTERRUPT_PIN_SHIFT)    | \
8589 	   (((line)&PCI_INTERRUPT_LINE_MASK)  <<PCI_INTERRUPT_LINE_SHIFT))
8590 
8591 #define	PCI_INTERRUPT_PIN_NONE			0x00
8592 #define	PCI_INTERRUPT_PIN_A			0x01
8593 #define	PCI_INTERRUPT_PIN_B			0x02
8594 #define	PCI_INTERRUPT_PIN_C			0x03
8595 #define	PCI_INTERRUPT_PIN_D			0x04
8596 #define	PCI_INTERRUPT_PIN_MAX			0x04
8597 
8598 
8599 
8600 /* Header Type 1 (Bridge) configuration registers */
8601 #define PCI_BRIDGE_BUS_REG		0x18
8602 #define   PCI_BRIDGE_BUS_PRIMARY_SHIFT		0
8603 #define   PCI_BRIDGE_BUS_SECONDARY_SHIFT	8
8604 #define   PCI_BRIDGE_BUS_SUBORDINATE_SHIFT	16
8605 
8606 #define PCI_BRIDGE_STATIO_REG		0x1C
8607 #define	  PCI_BRIDGE_STATIO_IOBASE_SHIFT	0
8608 #define	  PCI_BRIDGE_STATIO_IOLIMIT_SHIFT	8
8609 #define	  PCI_BRIDGE_STATIO_STATUS_SHIFT	16
8610 #define	  PCI_BRIDGE_STATIO_IOBASE_MASK		0xf0
8611 #define	  PCI_BRIDGE_STATIO_IOLIMIT_MASK	0xf0
8612 #define	  PCI_BRIDGE_STATIO_STATUS_MASK		0xffff
8613 #define	  PCI_BRIDGE_IO_32BITS(reg)		(((reg) & 0xf) == 1)
8614 
8615 #define PCI_BRIDGE_MEMORY_REG		0x20
8616 #define	  PCI_BRIDGE_MEMORY_BASE_SHIFT		4
8617 #define	  PCI_BRIDGE_MEMORY_LIMIT_SHIFT		20
8618 #define	  PCI_BRIDGE_MEMORY_BASE_MASK		0xffff
8619 #define	  PCI_BRIDGE_MEMORY_LIMIT_MASK		0xffff
8620 
8621 #define PCI_BRIDGE_PREFETCHMEM_REG	0x24
8622 #define	  PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT	4
8623 #define	  PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT	20
8624 #define	  PCI_BRIDGE_PREFETCHMEM_BASE_MASK	0xffff
8625 #define	  PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK	0xffff
8626 #define	  PCI_BRIDGE_PREFETCHMEM_64BITS(reg)	((reg) & 0xf)
8627 
8628 #define PCI_BRIDGE_PREFETCHBASE32_REG	0x28
8629 #define PCI_BRIDGE_PREFETCHLIMIT32_REG	0x2C
8630 
8631 #define PCI_BRIDGE_IOHIGH_REG		0x30
8632 #define	  PCI_BRIDGE_IOHIGH_BASE_SHIFT		0
8633 #define	  PCI_BRIDGE_IOHIGH_LIMIT_SHIFT		16
8634 #define	  PCI_BRIDGE_IOHIGH_BASE_MASK		0xffff
8635 #define	  PCI_BRIDGE_IOHIGH_LIMIT_MASK		0xffff
8636 
8637 #define PCI_BRIDGE_CONTROL_REG		0x3C
8638 #define	  PCI_BRIDGE_CONTROL_SHIFT		16
8639 #define	  PCI_BRIDGE_CONTROL_MASK		0xffff
8640 #define   PCI_BRIDGE_CONTROL_PERE		(1 <<  0)
8641 #define   PCI_BRIDGE_CONTROL_SERR		(1 <<  1)
8642 #define   PCI_BRIDGE_CONTROL_ISA		(1 <<  2)
8643 #define   PCI_BRIDGE_CONTROL_VGA		(1 <<  3)
8644 /* Reserved					(1 <<  4) */
8645 #define   PCI_BRIDGE_CONTROL_MABRT		(1 <<  5)
8646 #define   PCI_BRIDGE_CONTROL_SECBR		(1 <<  6)
8647 #define   PCI_BRIDGE_CONTROL_SECFASTB2B		(1 <<  7)
8648 #define   PCI_BRIDGE_CONTROL_PRI_DISC_TIMER	(1 <<  8)
8649 #define   PCI_BRIDGE_CONTROL_SEC_DISC_TIMER	(1 <<  9)
8650 #define   PCI_BRIDGE_CONTROL_DISC_TIMER_STAT	(1 << 10)
8651 #define   PCI_BRIDGE_CONTROL_DISC_TIMER_SERR	(1 << 11)
8652 /* Reserved					(1 << 12) - (1 << 15) */
8653 
8654 /*
8655  * Vital Product Data resource tags.
8656  */
8657 struct pci_vpd_smallres {
8658 	uint8_t		vpdres_byte0;		/* length of data + tag */
8659 	/* Actual data. */
8660 } __attribute__((__packed__));
8661 
8662 struct pci_vpd_largeres {
8663 	uint8_t		vpdres_byte0;
8664 	uint8_t		vpdres_len_lsb;		/* length of data only */
8665 	uint8_t		vpdres_len_msb;
8666 	/* Actual data. */
8667 } __attribute__((__packed__));
8668 
8669 #define	PCI_VPDRES_ISLARGE(x)			((x) & 0x80)
8670 
8671 #define	PCI_VPDRES_SMALL_LENGTH(x)		((x) & 0x7)
8672 #define	PCI_VPDRES_SMALL_NAME(x)		(((x) >> 3) & 0xf)
8673 
8674 #define	PCI_VPDRES_LARGE_NAME(x)		((x) & 0x7f)
8675 
8676 #define	PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID	0x3	/* small */
8677 #define	PCI_VPDRES_TYPE_VENDOR_DEFINED		0xe	/* small */
8678 #define	PCI_VPDRES_TYPE_END_TAG			0xf	/* small */
8679 
8680 #define	PCI_VPDRES_TYPE_IDENTIFIER_STRING	0x02	/* large */
8681 #define	PCI_VPDRES_TYPE_VPD			0x10	/* large */
8682 
8683 struct pci_vpd {
8684 	uint8_t		vpd_key0;
8685 	uint8_t		vpd_key1;
8686 	uint8_t		vpd_len;		/* length of data only */
8687 	/* Actual data. */
8688 } __attribute__((__packed__));
8689 
8690 /*
8691  * Recommended VPD fields:
8692  *
8693  *	PN		Part number of assembly
8694  *	FN		FRU part number
8695  *	EC		EC level of assembly
8696  *	MN		Manufacture ID
8697  *	SN		Serial Number
8698  *
8699  * Conditionally recommended VPD fields:
8700  *
8701  *	LI		Load ID
8702  *	RL		ROM Level
8703  *	RM		Alterable ROM Level
8704  *	NA		Network Address
8705  *	DD		Device Driver Level
8706  *	DG		Diagnostic Level
8707  *	LL		Loadable Microcode Level
8708  *	VI		Vendor ID/Device ID
8709  *	FU		Function Number
8710  *	SI		Subsystem Vendor ID/Subsystem ID
8711  *
8712  * Additional VPD fields:
8713  *
8714  *	Z0-ZZ		User/Product Specific
8715  */
8716 
8717 /*
8718  * Threshold below which 32bit PCI DMA needs bouncing.
8719  */
8720 #define PCI32_DMA_BOUNCE_THRESHOLD	0x100000000ULL
8721 
8722 #endif /* _DEV_PCI_PCIREG_H_ */
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